There are many areas of semiconductor device technology in which it is desired to dielectrically isolate devices fabricated on the same substrate from each other. Dielectric isolation is often desirable because it would, for example, permit higher packing density, that is, more devices could be fabricated per unit area. Accordingly, numerous techniques for obtaining dielectric isolation of devices fabricated on, for example, silicon, sapphire or gallium arsenide substrates, have been devised. Several exemplary techniques are described in the literature in the Journal of Electrochemical Society, 124, pp. 5c-12c, January 1977. The standardized dielectric isolation process described in this article with respect to FIG. 4 of this article unfortunately requires extensive lapping of a high perfection, thick and expensive silicon substrate although it provides good dielectric isolation. Several other methods described also require extensive lapping.
Another approach involves the growth of isolating oxide walls. For example, a technique commonly referred to as isoplanar has been developed. Channels are formed in epitaxial silicon and an oxide is then grown in the channel to isolate devices on opposite sides of the channel. This and other oxide growth methods have drawbacks. For example, silicon expands upon oxidation and a nonplanar oxide surface results and strains induced in the silicon may lead to device degradation. Thick oxide growth also requires holding the structure at high temperatures for extended periods of time. This can lead to undesirable dopant diffusion. Other methods that create channels in silicon and then fill the channels with oxide have also been developed but suffer from similar drawbacks.
Additional techniques have been developed and are described in the literature. For example, Japanese Journal of Applied Physics, 10, pp. 1675-1679, December 1971, describes a method for the selective epitaxial growth of silicon which uses a silicon nitride film as a mask disposed on a substrate. The silicon nitride film is deposited on the substrate, for example, silicon, and then selectively etched in those areas in which it is desired to grow epitaxial silicon to form the mask. The typical deposition technique is chemical vapor deposition, and deposition parameters, for example, pressure, are selected for which the silicon does not nucleate readily on the silicon nitride film. A typical deposition temperature for this technique is approximately 1250 degrees C. which again produces undesirable dopant diffusion. Another method for obtaining selective epitaxial growth is described in U.S. Pat. No. 3,574,008 issued on Apr. 6, 1971. The method is directed toward producing what the patentee refers to as a "Tier-type" configuration in which the side walls in a passivating layer are sloping. The desired flat surface requires lapping of the epitaxial silicon as material is not deposited on the partitions between epitaxial growth areas.
Methods for obtaining dielectric isolation have also been described for semiconductor materials other than silicon. For example, U.S. Pat. No. 3,928,092 issued on Dec. 23, 1975 to W. C. Ballamy and A. Y. Cho and assigned to Bell Telephone Laboratories, Inc. describes one such exemplary method. The method described forms a patterned amorphous surface having openings exposing a high quality substrate comprising a Group III-V compound. It is taught that when Group III-V compounds were deposited by molecular beam epitaxy that the material deposited on the single crystal material was single crystal and that the material deposited on the amorphous material was polycrystalline. The polycrystalline material has high resistivity and therefore the devices comprising single crystal Group III-V material are fabricated on the high quality substrate and are dielectrically isolated from each other. This method is, however, not useful with silicon because even polycrystalline silicon has relatively low resistivity.
Still another method developed to electrically isolate devices from each other is p-n junction isolation. However, in technologies such as CMOS (complementary metal oxide semiconductor) this requires a considerable amount of wafer surface area and complicated schemes are required to prevent latch-up.